Achronix Speedster22i Configuration Instrukcja Użytkownika

UG033, December 18, 2013 1 Speedster22i Configuration User Guide UG033 – December 18, 2013

10 UG033, December 18, 2013 In Figure 4 above: 1. After CONFIG_RSTN is deasserted, CPU_CLK needs to continue being clocked to ensure that the FPGA

UG033, December 18, 2013 11 SPI Flash Speedster22iHD FPGASCLKHOLDNDICSNDOSCKHOLDNSDICSN[0]SDO[0] Figure 6: Flash Connectivity to Speedster22iHD FPGA

12 UG033, December 18, 2013 SPI Flash Speedster22iHD FPGASCLKHOLDNDICSNDOSCKHOLDNSDICSN[0]SDO[0]SPI FlashSCLKHOLDNDICSNDOSPI FlashSCLKHOLDNDICSNDOS

UG033, December 18, 2013 13 JTAG JTAG configuration and operation mode is independent of CONFIG_MODESEL settings, although the recommendation is to en

14 UG033, December 18, 2013 Configuration Pins and Clock Selection Table 4 below lists the names and functions of all of the configuration and JTAG

UG033, December 18, 2013 15 1010103'b100CPU_CLKSYSCLKCONFIG_SYSCLK_BYPASSTCKCONFIG_MODESEL[2]CONFIG_MODESEL[1]CONFIG_MODESEL[0]CONFIG_CLKSELJTA

16 UG033, December 18, 2013 Bitstream File Generation Through ACE ACE has a straightforward interface to generate the bitstream files required to i

UG033, December 18, 2013 17 3. 4x Flash: A 4x Flash (.flash4x_0-3) binary file supporting configuration from 4 flash memory devices. This the same f

18 UG033, December 18, 2013 Design Security Speedster22iHD devices provide design security features using a 256‐bit Advanced Encryption Standard (A

UG033, December 18, 2013 19 3. Lower VCCFHV_EFUSE[3:1], VCCRAM_EFUSE[3:1] and VDDA_NOM_E/W all back down to 1.0V. Run phase 3 steps to validate the e

2 UG033, December 18, 2013 Copyright Info Copyright © 2013 Achronix Semiconductor Corporation. All rights reserved. Achronix is a tradema

20 UG033, December 18, 2013 Revision History The following table shows the revision history for this document. Date Version Revisions 12/18/2013 1.

UG033, December 18, 2013 3 Table of Contents Copyright Info ...

4 UG033, December 18, 2013 Overview The configuration architecture in Speedster22i HD devices is composed of a few key pieces: 1. Configuration pi

UG033, December 18, 2013 5 Power-Up and Configuration Sequence The requirements for the power-up and configuration sequencing for Speedster22i HD devi

6 UG033, December 18, 2013 powering up VDDL. Otherwise, with SRAM cells powering up in unknown states, the presence of one-hot muxes in the routing

UG033, December 18, 2013 7 The startup sequence consists of sequentially asserting a number of signals to ensure proper operation during user mode. Th

8 UG033, December 18, 2013 Configuration Modes and Pins Speedster22iHD devices have four configuration modes: CPU, Serial Flash x1, Serial Flash x4

UG033, December 18, 2013 9 CPU In CPU mode, an external CPU acts as the master and controls the programming operations for the FPGA. CPU mode is an 8-