Achronix Speedster22i SerDes Instrukcja Użytkownika

Speedster22i SerDes User Guide UG028 (v2.1) – July 1, 2014 UG028, July 1, 2014 1

Standards Variation Data Rate(s) QPI 4.8 Gbps 6.4 Gbps SATA SATA-1 1.5 Gbps SATA-2 3.0 Gbps SATA-3 6.0 Gbps SAS SAS-1 3.0 Gbps SAS-2 6.0 Gbps SAS-

The Ports of ACX_SERDES_SBUS_IF Module: The signals (ports) shown in “Figure 43 Changing Value of Register 17A to bypass PCS block” and “The Ports of

Example of SerDes Register Access through SBUS: Setting Loopback Mode The SerDes must be in the “ready” state before it enters loopback mode. Therefor

SerDes signals Sbus_clk and ready signals: The sbus_clk and ready signals must be connected between SerDes lane and ACX_SERDES_LOOPBACK_CTRL. The sbus

.i_pma_RXready(pma_RXready), ); // Use the IP Configuration Perspective in Ace to generate a Serdes wrapper gui_generated_serdes_wrapper iSERDES

Electrical Specifications Operating Conditions Table 22: Operating Conditions Parameter Notes Min Typical Max Unit DC Power-Supply Pin Requirements VD

Transmitter Table 23: DC and AC Switching Characteristics Parameter Description Min Typical Max Unit Output Eye Specification VTX-DIFF-PKPK Backporc

Parameter Description Min Typical Max Unit ZTX-DIFF-HIZ Transmitter Output Differential DC Impedance in Squelch Mode >2k Ω ZTX-CM-HIZ Transmitt

Table 25: Return Loss Standard Differential DC return loss Differential return loss at FBAUD/2 Common mode DC return loss Common mode return los

Receiver Table 26: DC and AC Switching Characteristics Parameter Description Min Typ Max Unit VRX-DIFF-PKPK Differential Input Peak to Peak Volta

Parameter Description Min Typ Max Unit ZRL-CM-NYQ Receiver Common-Mode Return Loss at Nyquist Frequency (FBAUD/2) -4 dB Receiver DC Impedance RDI

SerDes Placement The Speedster22i device supports up to sixty-four (64), 11.3 Gbps SerDes lanes. Each side (Top and Bottom) has thirty-two (32), 11.3

Parameter Description Min Typ Max Unit VRX-SENS Receiver Input Voltage Sensitivity Under the Following Conditions: • 50inch of FR4 • 6.25Gbps • P

Standard X1 (UI) X2 (UI) 2xVp-min (mV) 2xVp-max (mV) OIF CEI 6G – LR 0.475 0.5 N/A 1200 FC-1 0.33 0.5 275 2000 FC-2 0.35 0.5 275 2000 FC-4 0.33 0.5

Reference Clock The electrical specifications for the reference clock are summarized in the following tables Table 29: Reference Clock Electrical Spef

Revision History The following table shows the revision history for ths document. Date Version Revisions 3/29/2013 1.0 First customer release 4/22/2

SerDes Architecture Overview The SerDes has an independent lane architecture. Each lane has a Physical Media Attachment (PMA), Synthesizer (Transmit P

Physical Media Attachment (PMA) The PMA architecture is shown in “Figure 3: PMA Architecture” below. Figure 3: PMA Architecture The PMA consists thre

2. Receiver (RX)/Transmitter (TX) The RX/TX block consists of the following circuits: • TX buffer: Converts single-ended signal to differential and

Figure 5: Receiver Architecture UG028, July 1, 2014 15

PCS Blocks in the Transmitter (TX) This section presents the transmitter (TX) data path within a PCS. The key blocks within the SerDes transmitter ar

Polarity and Bit Inversion – 10/20 bit Operation When operating in 10bit/20bit mode, the bit order within each 10-bit word can be inverted. This is il

Polarity and Bit Inversion – 8/16 bit Operation When the polarity is inverted in 8bit/16bits mode, only bits [17:10] and [7:0] are inverted, bits [19:

Figure 11: Word Order Inversion (16-bit Word) UG028, July 1, 2014 19

Table of Contents List of Figures ...

Interface Encapsulation This block encapsulates the protocols supported by the SerDes in Achronix FPGA. The user may refer to Section – “PCS Interface

The input disparity for the 6 bit block is based on the disparity of previous word’s 4 bit block while the disparity for the 4 bit block is the dispar

PCS Blocks in the Receiver (RX) This chapter describes the PCS components on the receiver data path. The functional block diagram of the receiver is

Equation 1:  = (   ) +  

Modes of Operation Manual Mode: In manual alignment mode, the symbol alignment will attempt to identify a pre-configured pattern and lock to the inco

Deskew FIFO The deskew block provides support for standards which require multiple lane bonding and de-skewing of received data across multiple lanes.

Functional Description The de-skew block uses a deskew FIFO on each lane. The writes to the deskew FIFO are performed in the recovered clock domain fo

Symbol slip mode: The deskew module does not actively remove skew across lanes. Each lane is controlled by the fabric. Fabric continuously monitors i

EFIFO Standards and Skip Characters PCIe Gen3: To support PCIe Gen3, 4-bytes of skip are added at byte positions 4-7 from the sync header associated w

EFIFO Operation “Figure 15: EFIFO SKP Addition/Removal” illustrates the process of SKP addition/removal. Figure 15: EFIFO SKP Addition/Removal In “F

The deskew module can work in three modes: ... 26 Standards

“Figure 16: EFIFO SKP Addition/Removal: PCIE, GigE (802.3) and XAUI (802.3)” illustrates SKP additions and removals for PCIe, GigE (802.3), and XAUI (

Overflow/Underflow If the difference between the write and read counters is greater than fifo_full, then the overflow signal is asserted. If the diffe

the 20-bit mode of operation, the most significant 20-bits of data are placed on bits 19:0 of the barrel shifter and the least significant 20-bits are

PCS Interface The PCS interface provides the general interface between the PCS and the core fabric. The PCS supports the following interfaces: • Giga

XAUI The PCS supports XAUI compliant with section 48 of IEEE 802.3. The Protocol block implements the Transmit and Receive state machines as per Figur

The 128b/130b encoder is disabled on power up, and enabled when the rate bits coming from the MAC are configured to 2’b10. The PCS layer support for P

Clocking “Figure 17: SerDes RX and TX clocks” gives an overview of the clocks inside the SerDes. The PMA of a SerDes lane generates two clocks, a TX

Although each lane has its own clock output pins to the fabric, with lane bonding these are all just route-throughs of the master clock: regardless of

Debug and Test The SerDes comes integrated with a wide range of debug and test features for excellent coverage. The following features are provided:

PMA loopback modes: Figure 18: PMA Loopback Modes PCS loopback modes: Figure 19: Looback modes Please refer “Dynamic Read/Write of SerDes Registe

RX PCS Settings ...

PMA Test Pattern Generator The PMA supports a built in transmit data pattern generator that can be used for transmit characterization. The test patter

The transmit pattern generator can optionally transmit user defined patterns instead of PRBS patterns, configured through the control registers. Two

Latency This section presents the worst case latency for PMA and PCS blocks. PMA Latency The following equation calculates the worst-case latency for

“Table 9: Latency across the PCS blocks” presents the latency experienced by datapath in these two modes. The worst case latency is presented in in “F

Figure 20 Worst-case latency across PMA and PCS (in terms of clock-cycles) 44 UG028, July 1, 2014

Configurations Supported Table 10: Supported Transmitter (TX) Features Standard Variation Data Rates (Gbps) Number of Lanes Suggested Reference C

Standard Variation Data Rates (Gbps) Number of Lanes Suggested Reference Clock (MHz) Parallel Data Width (Bits) Encoder PBR Out-of-Band OC-24 1.2

Table 11: Supported Receiver (RX) Features Standard Variations Data Rates (Gbps) Symbol Align PBR Transition Density Checker Clock Compensation (E

Standard Variations Data Rates (Gbps) Symbol Align PBR Transition Density Checker Clock Compensation (EFIFO) Lane De-skew Decoder Bit Slider 10GFC 1

Design Flow: Creating a SerDes Design In this chapter, step-by-step instructions for creating a SerDes design are presented: 1. Generation of SerDes

List of Figures Figure 1: Location of SerDes Lanes ...

The user is assumed to have basic understanding of using ACE GUI. The user may refer to the online demo as well as the ACE documentation for different

To generate a SerDes wrapper, the user will need to double click on the link 12G SerDes in IP Libraries window. This will bring up the window for crea

Figure 23: New IP Configuration Window- Overview Page The user will now have the Overview page in the main window with the options for entering desi

Overview Section: Initially, the main window in the middle will contain the Overview page as shown in Figure 26: New IP Configuration Window – Popula

Entry field Purpose Available Options Choice made Number of Lanes Number of lanes used by the design 1 to 12. 1 TX Data Rate (Gbps) TX data rate fo

Entry field Purpose Available Options Choice made SerDes Lanes The specific lane used. Achronix FPGA has 64 SerDes lanes, 32 each on North and South

Figure 27: Issues with Setting TX/RX data rate and reference clock frequency 56 UG028, July 1, 2014

Figure 28: Unavailable Fields As “Figure 28: Unavailable Fields” shows Some fields become unavailable based on earlier choices made by the user. In t

Figure 29: PMA Settings Window – First page The first page of the PMA Settings section gives the options to enter lane-specific PMA settings. This

Figure 30: Outline Window, When Lane-Specific PMA Settings are Enabled RX PMA Equalization This page allows the user to change the PMA equalization

List of Tables Table 1: SerDes Standards...

Entry field Purpose Available Options* Choice made High Freq AGC AC Boost Control AC boost of High frequency AGC 32 options ranging from 0.4 dB to 18

Table 14: RX PMA PLL Settings Entry field Purpose Available Options Choice made RX PPM Controls the frequency accuracy threshold (ppm) for lock dete

TX PMA Driver This page allows the user to configure the transmit driver settings on PMA.. The entry fields and the available options are listed in “T

Table 16: TX PMA PLL Settings Entry field Purpose Available Options Choice made TX PPM Configure the PPM difference between reference clock and divi

Figure 32: PCS Settings for Receiver – Default Settings RX PCS Settings This page allows the user to configure the RX PCS settings. The entry fields

Entry field Purpose Available Options Choice made Elastic FIFO*3 Use Elastic FIFO*3 Whether clock compensation block on PCS (i.e., EFIFO) will be use

RX PCS Symbol Alignment “Figure 33: PCS Settings for Receiver – Symbol Alignment” presents the RX PCS Symbol Alignment window with the choices pertain

Entry field Purpose Available Options Choice made Word 0 Value of Word# 0, when enabled. Text field to enter user-defined value (available when Word

Entry field Purpose Available Options Choice made Alt Seq 1 Text field to enter user-defined value (available when Alt Seq 0 is enabled) N/A since Al

Table 19: TX PCS Settings Entry field Purpose Available Options Choice made Encoder • Disabled • 8b/ 10b • 128/130b 8B10B PBR Functions PBR

Chapter 1 – SerDes Architecture Overview Achronix Speedster22i FPGAs provide very high core fabric and I/O performance which exceeds the system bandwi

Generation of Wrapper Files: The user can now generate wrapper files (src/ace folder) by clicking the Generate button. Note: The user can generate th

If the files are successfully generated, the user will find the corresponding message on the TCL sub-window, as shown in “ Figure 36: TCL console mes

Integration of SerDes Wrapper in a Design This section details how to use the files generated by ACE GUI into a user-design. For ready-reference, the

iSerDes is chosen as the Hierarchical Instance Path, the generated .sdc and .pdc files need not be modified. “Table 20: Signals passed between the Ser

SerDes Port Name Top-level Signal-name Comments whether the SerDes is ready. For instance, ln0_TX_ready indicates that the SerDes is ready for data re

Dynamically Changing the SerDes Register Values Typically the PMA/PCS registers need not be changed during runtime. However, simple_serdes_design use

.i_reg_wr_data (unused_ln0_i_reg_wr_data), // data for write .o_reg_rd_data (unused_ln0_o_reg_rd_data), // data

Note: When 10’h1BC is transmitted from the fabric, the output of the 8b/10b decoder on the PCS receiver path will be 10’h283 (alternate: 10’h17C). Th

the placement of SerDes-Reset signal (ln0_rst_hard); TX-ready status signal (ln0_TX_ready) and the placement of the sbus-clock that is required to se

create_generated_clock iSERDES.x_ch0.iffdmux.GEN_CLKDIV.TX.iTXclkdiv/clk_out –source iSERDES.x_ch0.u_serdes_wrap.u_serdes/o_TX_data_clk -divide_by 2

o Programmable spread spectrum generation o Support for 16-bit fractional multiplication factors o Programmable spread spectrum clocking o Suppor

Design Guidelines This section will first present the coding practice that the user is recommended to use. Reset Sequence The following sequence is pr

• All clocks from SerDes lanes 0 to 14 on the South Side of the Chip enter the far SouthWest clock region. • All clocks from SerDes lanes 20 to 31 o

Figure 37: Clock Region View 82 UG028, July 1, 2014

The following factors determine how many clocks enter the Core for each SerDes lane or bonded group of lanes: • Use of Hard IP Controllers: If you ar

• SerDes lanes on the chip are divided into physical groups of 8 lanes (0-7), 12 lanes (8-19) and 12 lanes (20-31) on the North and South sides of th

Figure 39: SerDes Placement Guidelines • Avoid lanes 15-19 (on North and South) when not using channel bonding, since these lanes consume clock res

lanes. Now we have a total of 4 clocks per bonded group of 12 lanes, or 8 total clocks for the 24 10 Gbps lanes. At this point, we have a total of 16

Design Tips Timing report of a routed design: When a design passes through the place-and-route tool, please make sure that there is no setup- and/or

For our sample design, we have defined data-rate=10.3125gbps and data-width=20. For this higher-rate, the wide-bus architecture will be used. In othe

Overview of the modification: With respect to the steps followed in creating simple_serdes_design, the following modifications are made in preparing

Major standards supported Table 1: SerDes Standards Standards Variation Data Rate(s) PCI Express Gen1 2.5 Gbps Gen 2 5.0 Gbps Gen 3 8.0 Gbps Giga

Entry field Available Options Choice made Eanble ALT 0*3 • True • False True ALT SKIP Word 0*3 Text field to select user-defined value (available on

Figure 40: PCS Settings for Receiver – Configurations for Decoder and Elastic FIFO Now, just as we did for the design without clock-compensation (

Related modifications are listed below: Simple_serdes_design_efifo_wrapper iSerDes ( // ============================= // Lane 0 // ***************

Modification – 3 (placement and timing constraints): Since there is only one divide-by-two clock in this derivative of the design, we can remove the p

Note: Although the PCS modules are disabled, the SerDes will still generate two clocks for transmit and receive ends (from PMA). Unlike the design wit

Note: When compared with the sample design (simple_serdes_design), no change is required in ace_placement.pdc or in ace_constraint.sdc files for this

Figure 42: Modifying Register Settings from ACE GUI To bypass the PCS block, the bit-4 of Reg[17A] needs to be set to 1’b1, i.e., 17A needs to be se

Figure 43: Changing Value of Register 17A to bypass PCS block Note: Setting Reg[17A] at 8’h10 will automatically disable all PCS modules even if the

Dynamic Read/Write of SerDes Registers via SBUS This chapter broadly categorizes the PMA and PCS registers into: 1. Static registers 2. Dynamic regi

ACX_SERDES_SBUS_IF Module The connection diagram for ACX_SERDES_SBUS_IF is shown in “Figure 44 Disabling PCS Decoder (default ACE Setting)”. Figure 44