Achronix Speedster22i Pin Connections and Power Sequencing Instrukcja Użytkownika Pobierz pdf (Strona 12)

12 UG042, August 19, 2014

Power Sequencing Block Diagram

Power Up Requirements

VCC, VDD_CFG, VDD_BRAM

VDD_CFGWL

VDDO_B[xx] (1.2V/1.5V/1.8V)

VDDO_JCFG

AVDD_PLL

VDDA_NOM_E/W

VCCRAM/FHV_EFUSE

PA_VDD1

PA_VDD2

Begin powering up

PA_VDD1 and

PA_VDD2 after VCC

is fully powered-up

Power these down

before the other

supplies

Config_status

VDDL

Begin powering up VDDL after

Config_status goes high

Power Down Requirements

VCC, VDD_CFG, VDD_BRAM

VDD_CFGWL

VDDO_B[xx] (1.2V/1.5V/1.8V)

VDDO_JCFG

AVDD_PLL

VDDA_NOM_E/W

VCCRAM/FHV_EFUSE

PA_VDD1

PA_VDD2

Config_status

VDDL

Config_rstn

Assert config reset after

VCC, PA_VDD1/2

come up

Config_status released

some time after device

comes out of reset

1 2 ... 7 8 9 10 11 12 13

Copyright Info 2
Pin Connection Guidelines 3
IEEE1149.1 JTAG Interface 4
Configuration Interface 4
Clock I/O Interface 7
Miscellaneous 8
UG042, August 19, 2014 9
Power Supply Block Diagram 11
Power Up Requirements 12
Power Down Requirements 12
Revision History 13

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Achronix Speedster22i Pin Connections and Power Sequencing Instrukcja Użytkownika Strona 12

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