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Achronix Speedster22i User Macro Guide Instrukcja Użytkownika Strona 145

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Memories BRAM80KFIFO
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 128
Table 6-27: Reset Usage Model for wrrst and rdrst Inputs
Use Model
Required wrrst and rdrst
c
onnections
Required
wrrst_input_mode
assignme
nt
Required
rdrst_input_mode
assignment
A single reset in the rdclk domain
resets both the read and write
pointers.
The user reset is connected to the
rdrst input. The wrrst signal is tied
inactive.
2’b11 2’b00
A single reset in the wrclk domain
r
esets both the read and write
pointers.
The user reset is connected to the
wrrst input. The rdrst signal is tied
inactive.
2’b00 2’b11
A single asychronous reset resets
both the
read and write pointers.
The user reset is connected to
both the wrrst and rdrst inputs.
2’b11 2’b11
The wrrst reset in the wrclk
domain or the r
drst reset in the
rdclk domain resets both the read
and write pointers.
The user reset in the wrclk domain
i
s connected to the wrrst input.
The user reset in the rdclk domain
is connected to the rdrst input.
2’b10 2’b10
The wrrst reset in the wrclk
domain r
esets the write pointer.
The rdrst reset in the rdclk domain
resets the read pointer.
The user reset in the wrclk domain
i
s connected to the wrrst input.
The user reset in the rdclk domain
is connected to the rdrst input.
2’b00 2’b00
wrrst_sync_stages
The wrrst_sync_stages parameter defines the number of stages of registers used to
synchronize the wrrst input pin to the rdclk clock domain if the wrrst signal is usedbythe
Read Pointer Reset. The value of the wrrst_sync_stages parameter is only used if the
rdrst_input_modeissetto2’b10or2’b11.Themappingofthewrrst_sync_stagesparameter
va
lue to the number of sychronization stages is defined in Table 6‐28
: Mapping
wrrst_sync_stages Parameter Sett
ings to Synchronization Stage Depth, where each stage
corresponds to a re
gister in the Write Reset Synchronizer shown in Figure 6‐9: Read and
WritePo
interResetInputSelectionBlockDiagram.Forexample,settingwrrst_sync_stages
to2’
b00configuresthewrrstsynchronizationcircuittohavetwoback‐to‐backregistersinthe
WriteResetSynchonizer.Thedefaultvalueofthewrrst_sync_stagesparameteris2’b00.
Table 6-28: Mapping wrrst_sync_stages Parameter Settings to S
ynchronization Stage Depth
wrrst_sync_stages Write Reset Synchronization Stage Depth
2’b00 2
2’b01 3
2’b10 4
2’b11 5
wrptr_sync_stages
The wrptr_sync_stages parameter defines the number of stages used in the Write Pointer
SynchonizercircuitthatsynchronizestheWritePointertotherdclkclockdomain.Whenthe
FIFO is in asynchronous mode, (sync_mode = 1’b0), the output of the synchonized Write
Pointeriscomparedtothe ReadPointertogeneratetheemptyandalmost_emptyfl
ags.The
synchronizedWritePointermayalsoberoutedtothewrcounteroutput(wrcount_sync_mode
= 1’b0). The mapping of the wrptr_sync_stages parameter value to the number of sychro ‐
nizationstagesisde
finedinTable6‐29: Mappingwrptr_sync_stagesParameterSettingsto
SynchronizationStageDe
pth,whereeachstagecorrespondstoaregisterintheWritePointer
Synchronizer circuit sho
wn in Figure 6‐10: Write Pointer Synchronizer Block Diagram.
Higher va
lues forthe wrptr_sync_stages parameter reduce the possibility of a metastable
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