Achronix Speedster22i User Macro Guide Instrukcja Użytkownika Pobierz pdf (Strona 206)

Table 9-1: Ports

Name Type Description

refclk

Reference Clock. The

reference clock, which is optionally divided

by the Reference Divider, is fed into the Phase Frequency Detector.

The input to the Phase Frequency Detector must be in the range of

30 MHz to 400 MHz.

fbclk

Feedback Clock. T

he user may connect the Feedback Clock to one

of the generated clkout[3:0] outputs so that the PLL may compen-

sate for the delay of the clock network.

rstn

PLL Reset. S

etting the rstn input low will reset the PLL. After return-

ing the rstn input to a high level, th

e PLL should lock within 500 ref-

clk (after the Reference Divider) clock periods if the PLL

is used in

integer divider mode and 1000 clock periods if the PLL is used in

fractional divider mode. The user must hold rstn low for at least one

cycle of the clock frequency input into the Phase Frequency Detec-

tor (after the Reference Divider).

outphrstn

Output Phase Reset. S

etting the rstn input low will reset the Phase

Rotator to its initial startup value.

core_clken[3:0]

Clock Output Enable. Th

e core_clken[3:0] controls if the clock out-

puts of the PLL are being driven. Setting the clock enable bit to one

enables the clock

output of the corresponding bit position.

phase_inc[3:0]

Clock Phase Increment. A

low to high transition of the phase_inc

input increments the phase adjustment of the addressed Phase

Rotator by 1/8th of the VCO frequency. The high period of the

phase_inc signal must be at least at half of the output frequency.

clkout[3:0] Clock Output.

pll_lock

PLL Lock Status. A

high level on the pll_lock signal indicates that

the PLL is locked.

ick_dspll_sif_clk Serial Control Bus Clock (o

ptional).

ick_dspll_sif_rstn Serial Control Bus Reset (o

ptional).

ick_sbus_data Serial Control Bus Data Input (optio

nal).

ick_sbus_req Serial Control Bus Request (o

ptional).

ock_sbus_ack Serial Control Bus Acknowledge (o

ptional).

ock_sbus_data Serial Control Bus Data Output (optio

nal).

PLL/DLL Clock Generators ACX_CLKGEN

Speedster Macro Cell Library

www.achronix.com PAGE 189

ACX_CLKGEN Pins

input

output

input

output

1 2 ... 201 202 203 204 205 206 207 208 209 210 211 ... 223 224

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