Achronix Speedster22i User Macro Guide Instrukcja Użytkownika Pobierz pdf (Strona 35)

I/O Cells IPAD_D2

Speedster Macro Cell Library

www.achronix.com PAGE 18

Table 1-21: Parameters

Parameter Defined Values Default Value

location

iostandard “LVCMOS18”

drive

rstmode

rstvalue

slew

keepmode

hysteresis

open_drain “true”, “false” “false”

pvt_comp “none”, “own” “none”

odt “off ”, “on” “off ”

termination “50”, “60”, “75”, “100”

, “120”, “240” “50”

Figure 1-9: IP

AD_D2 Input Timing Diagram (assumes data_en = 1’b1)

Verilog Instantiation Template

IPAD_D2 #(.location(""),

.iostandard("LVCMOS18"),

.drive("16"),

.rstmode("async"),

.rstvalue("low"),

.hysteresis("none"),

.pvt_comp("none"),

.termination("50"),

.odt("off"))

instance_name (.pad(user_pad), .douta(user_douta), .doutb(user_doutb),

.data_en(user_data_en)

, .txrstn(user_txrstn), .rxrstn(user_rxrstn),

.rstn(user_rstn), .clk(user_clk));

VHDL Instantiation Template

------------- ACHRONIX LIBRARY ------------

library speedster22i;

use speedster22i.components.all;

------------- DONE ACHRONIX LIBRARY ---------

-- Component Instantiation

IPAD_D2_instance_name : IPAD_D2

generic map (location => ““,

ostandard => “LVCMOS18”,

rstmode => “async”,

rstvalue => “low”,

“<pad_location>” ““

See Table1‐1

"2", "4", "6", "8", "12", "16" "16"

“sync”, “async” “async”

“low”, “high” “low”

“fast”, “slow” “slow”

"pullup", "pulldown", "none" “none”

"none", "schmitt" “none”

clk

douta

doutb

pad

1 2 ... 30 31 32 33 34 35 36 37 38 39 40 ... 223 224

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