Achronix Speedster22i User Macro Guide Instrukcja Użytkownika Pobierz pdf (Strona 96)

Registers DFFR

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 80

Table 2-48: Function Table when sr_assertion = “unclocked

Inputs Output

rn d ck q



’

Table 2-49: Function Table when sr_assertion = “clocked

Inputs Output

rn d ck q



’

Verilog Instantiation Template

DFFR #(.init(1’b0))

instance_name

(.q(user_out),

.d(user_din),

.rn(user_reset),

.ck(user_clock));

VHDL Instantiation Template

------------- ACHRONIX LIBRARY ------------

library speedster22i;

use speedster22i.components.all;

------------- DONE ACHRONIX LIBRARY ---------

-- Component Instantiation

DFFR_instance_name : DFFR

generic map (

init => ‘0’)

port map (q => user_out,

d => user_din,

rn => user_reset,

ck => user_clock);

0X X 0

1X XHold

10 0

11 1

0X  0

XHold

10 0

11 1

1 2 ... 91 92 93 94 95 96 97 98 99 100 101 ... 223 224

Brak uwag

Achronix Speedster22i User Macro Guide Instrukcja Użytkownika Strona 96