Achronix Speedster22i User Macro Guide Instrukcja Użytkownika Pobierz pdf (Strona 52)

I/O Cells OPAD_DIFF

Speedster Macro Cell Library

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OPAD_DIFF

Non-Registered Differential Output Pad

din

pad

OPAD_DIFF

padn

Figure 1-18: OPAD_DIFF Logic Symbol

OPAD_DIFFis anasynch

ronousdifferentialoutputpadwithinputdinandoutputspadand

padn.

Table 1-39: Ports

Name Type Description

din Data input.

pad Device output pad. T

he data at the din input is driven to the pad output.

padn

Device complement output pad. The

logical inverse of the data at the din

input is driven to the padn output.

Table 1-40: Parameters

Parameter Defined Values Default Value

locationp

locationn

iostandard “LVDS”

drive

slew

open_drain “true”, “false” “false”

pvt_comp “none”, “own” “none”

invert_out “off ”,”on” “off ”

Table 1-41: Output Function Table

din pad padn

Verilog Instantiation Template

OPAD_DIFF #(.locationp(""),

.locationn(""),

.iostandard("LVDS"),

.drive("16"),

.slew("slow"),

.invert_out(“off”),

.open_drain(“false”),

.pvt_comp("none"))

input

output

“<pad_location>” ““

See Table1‐2

"2", "4", "6", "8", "12", "16" "16"

“fast”, “slow” “slow”

00 1

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 223 224

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