Achronix Speedster22i User Macro Guide Instrukcja Użytkownika Pobierz pdf (Strona 201)

Speedster Macro Cell Library www.achronix.com PAGE 184

Chapter 8 – Special Functions

ACX_DESERIALIZE (Speedster22iHP Only)

1:N Serial-to-Parallel Converter

q[output_width - 1 : 0]

ACX_DESERIALIZE

ACX_DESERIALIZEimplementsan1:Nserial‐to‐parallelconversionofthedatainput,where

Nisspecifiedbythe output_width parameter. Theparalleloutput stream, q, is output at N

timesslowerthanthefrequencyofclk.Thedeserializeddataisplacedintotheparalleloutput

starting with the least significant bit and pr

oceeding to the most significant bit.

ACX_DESERIALIZEmaybeusedtoreducedtherateatwhichdataisdrivenoffthedeviceif

theinternalprocessingrateexceedsthefrequencyratingofthedeviceI/Os.Thisblockmaybe

usedinconjunctionwithACX_SERIALIZEtoperformtheinitialserializationprocess.

Table 8-1: Pin Description

Name Type Description

d Data input.

clk Clock.

q[output_width –1 : 0]

Parallel data output. T

he value on the q output is filled start-

ing with the LSB and proceeding t

o the MSB. The output data

division rate must be specified by the output_width parameter.

Table 8-2: Parameters

Parameter Defined Values Default Value

output_width

Verilog Instantiation Template

ACX_DESERIALIZE #(.output_width(4))

instance_name(.q(user_q[output_width -1 : 0]),

.d(user_d),

.clk(user_clk));

Figure 8-1: Logic Symbol

input

output

positive integers 4

1 2 ... 196 197 198 199 200 201 202 203 204 205 206 ... 223 224

Brak uwag

Achronix Speedster22i User Macro Guide Instrukcja Użytkownika Strona 201